We present an algorithm for two- and three-dimensional capacitance analysis on multidielectric integrated circuits of arbitrary geometry. Our algorithm is stochastic in nature and as such fully parallelizable. It is intended to extract capacitance entries directly from a pixelized representation of the integrated circuit (IC), which can be produced from a scanning electron microscopy image. Preprocessing and monitoring of the capacitance calculation are kept to a minimum, thanks to the use of distance maps automatically generated with a fast marching technique. Numerical validation of the algorithm shows that the systematic error of the algorithm decreases with better resolution of the input image. Those features render the presented algorithm well suited for fast prototyping while using the most realistic IC geometry data.